Towards a generic programming model for network processors

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Lee, K. ORCID: 0000-0002-2730-9150, Coulson, G., Blair, G., Joolia, A. and Ueyama, J., 2004. Towards a generic programming model for network processors. In: Proceedings: 12th IEEE International Conference on Networks (ICON 2004) [volume 2], Singapore, 16-19 November 2004. Los Alamitos, California: IEEE Computer Society, pp. 504-510. ISBN 078038783X

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Official URL: http://dx.doi.org/10.1109/ICON.2004.1409218

Abstract

Network Processors (NPs) are emerging as a cost effective network element technology that can he more readily updated and evolved than custom hardware or ASIC-based designs. Moreover, NPs promise support for run-time reconfiguration of low-level networking software. However, it is notoriously difficult to develop software for NPs because of their complex design, architectural heterogeneity, and demanding performance constraints. In this paper we present a runtime componentbased approach to programming NPs. The approach promotes conceptual uniformity and design portability acros a wide variety of NP types while simultaneously exploiting hardware assists that are specific to individual NPs. To show how our approach can be applied in a wide range of types of NPs we characterise the design space of NPs and demonstrate the applicability of our concepts to the various classes identified. Then, as a detailed case study, we focus on programming the Intel IXP1200 NP. This demonstrates that our approach can be effectively applied, e.g. in terms of performance, in a demanding real-world NP environment.

Item Type:

Chapter in book

Creators:

Lee, K., Coulson, G., Blair, G., Joolia, A. and Ueyama, J.

Publisher:

IEEE Computer Society

Place of Publication:

Los Alamitos, California

Date:

2004

ISBN:

078038783X