Network on chip architecture for multi-agent systems in FPGA

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Gerlein, E.A., McGinnity, T.M. ORCID: 0000-0002-9897-4748, Belatreche, A. and Coleman, S., 2017. Network on chip architecture for multi-agent systems in FPGA. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 10 (4), p. 25. ISSN 1936-7406

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Official URL: http://doi.org/10.1145/3121112

Abstract

A system of interacting agents is, by definition, very demanding in terms of computational resources. Although multi-agent systems have been used to solve complex problems in many areas, it is usually very difficult to perform large-scale simulations in their targeted serial computing platforms. Reconfigurable hardware, in particular Field Programmable Gate Arrays (FPGA) devices, have been successfully used in High Performance Computing applications due to their inherent flexibility, data parallelism and algorithm acceleration capabilities. Indeed, reconfigurable hardware seems to be the next logical step in the agency paradigm, but only a few attempts have been successful in implementing multi-agent systems in these platforms. This paper discusses the problem of inter-agent communications in Field Programmable Gate Arrays. It proposes a Network-on-Chip in a hierarchical star topology to enable agents’ transactions through message broadcasting using the Open Core Protocol, as an interface between hardware modules. A customizable router microarchitecture is described and a multi-agent system is created to simulate and analyse message exchanges in a generic heavy traffic load agent-based application. Experiments have shown a throughput of 1.6Gbps per port at 100 MHz without packet loss and seamless scalability characteristics.

Item Type:

Journal article

Publication Title:

ACM Transactions on Reconfigurable Technology and Systems (TRETS)

Creators:

Gerlein, E.A., McGinnity, T.M., Belatreche, A. and Coleman, S.

Publisher:

Association for Computing Machinery

Date:

22 November 2017

Volume:

Number: