Communication interfaces for a distributed embedded multiprocessor system

Chin, W.K., 2007. Communication interfaces for a distributed embedded multiprocessor system. PhD, Nottingham Trent University.

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This thesis documents a research project on communication interfaces for a distributed embedded multiprocessor system. This resulted in the development of a novel embedded distributed multiprocessor system on a single chip.

The initial feasibility studies involved a review of the relevant embedded distributed multiprocessor systems and their inter-processor communication. The research aimed to expand the potential of a multiprocessor communication system on a single chip. System designs were adapted to achieve more efficient Direct Memory Access (DMA) and reduced processor intervention.

A development board with advanced FPGA technology is used to implement the designed modules. The single chip solution consists of two processing nodes and an 'off- the-shelf hardware message router. Each processing node includes: a NIOS II processor, a memory module, and a network interface controller. The network interface controller, which interconnects the processor and the embedded routing network, was developed using VHDL.

All basic routing features and functions of this novel VHDL system model have been proven and verified through hardware testing and simulation. The system was synthesised and implemented into a single FPGA chip as a System-on-Programmable- Chip (SOPC). A test program was written to test the functionality of the interface. The research resulted in a fully operational prototype. The features of the system are discussed and compared and contrasted with the state-of-the-art research literature.

The router and NIOS II processors with their interface form the building blocks of a robust, embedded network on the single chip platform. The router interconnects all the processing nodes and allows them to operate in the same network simultaneously, thus increasing system flexibility and applications. The in-built differential output feature on the FPGA chip enables the system to be cascaded to more processing nodes off-chip.

Item Type: Thesis
Creators: Chin, W.K.
Date: 2007
ISBN: 9781369314717
Divisions: Schools > School of Science and Technology
Record created by: Linda Sullivan
Date Added: 21 Sep 2020 15:17
Last Modified: 28 Jul 2023 14:36

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