FPGA design and development of a digital video broadcasting (DVB) based channel encoder using VHDL

Chuah, K.H., 2005. FPGA design and development of a digital video broadcasting (DVB) based channel encoder using VHDL. MPhil, Nottingham Trent University.

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This research thesis presents a cost effective implementation of Digital Video Broadcasting (DVB) based channel encoder, using Field Programmable Gate Array (FPGA), for an experimental 42 GHz Multimedia Wireless System (MWS): The Nottingham Trent University Campus Network Trial System.

This thesis details investigations and the subsequent design and testing of a channel encoder for the 42 GHz MWS network trial. This includes identifying an FPGA as the development platform; examining, verifying and implementing off-the-shelf Intellectual Property (IP) cores as part of the encoder design. Control algorithms were designed to ensure reliability of data-flow processes. The channel encoder also reconditions the transport packets, for compatibility between system modules and the IP core. Functional modules were coded separately using hardware description language and finally integrated as a system aided by Electronics Design Automation.

As this channel encoder is part of the DVB-Satellite (DVB-S) physical layer that can be evaluated on the 42 GHz campus network experimented test-bed, standard interfaces between systems were used and the encoder specifications were in compliance with the DVB-S standard, to work with off-the-shelf DVB-S set-top-boxes (STBs). Device input/output electrical characteristics were also investigated and adapted to the system. Taking advantage of the flexibility of FPGAs, a combination of Forward Error Correction (FEC) coding schemes were made available that can be reconfigured to be applied to the radio channel. The final FPGA compilation shows a total of 1,461 logic elements and 15,616 memory bits being used on the Cyclone EP1C6Q240C6 device.

The hardware was tested, operating at 26.666 Mbaud for an FEC code rate of 3/4 and 40.000 Mbaud for an FEC code rate of 1/2. The complete end-to-end system was verified using both emulated and 'live' digital television transport multiplex. The status register of a satellite STB was used to confirm its functionality.

This research has resulted in an inexpensive implementation of a DVB channel encoder for millimetre-wave broadband fixed wireless access offering television broadcasting and interactive data services. The channel encoder was programmed onto an FPGA and has been effectively tested as part of the campus network trial. Further development anticipates dynamic reconfiguration with adaptive capabilities.

Item Type: Thesis
Creators: Chuah, K.H.
Date: 2005
ISBN: 9781369324464
Rights: This copy of the thesis has been supplied on condition that anyone who consults it is understood to recognise that its copyright rests with the author and that no quotation from this thesis and no information derived from it may be published without the author's prior written consent.
Divisions: Schools > School of Science and Technology
Record created by: Linda Sullivan
Date Added: 12 Nov 2020 14:08
Last Modified: 12 Oct 2023 09:53
URI: https://irep.ntu.ac.uk/id/eprint/41640

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